MRAM is a type of random access memory that stores information not as an electric charge but in the magnetic state of a cell. It combines the high speed of RAM with the non-volatility of flash storage, retaining data when power is turned off and providing a virtually unlimited rewrite endurance.
Typical applications of MRAM include aerospace and defense industries, industrial automation, and automotive systems, where data retention during sudden power loss is critical. The technology is used in controllers for storing critical parameters, flight recorders, Internet of Things devices, and implantable medical electronics. In recent years, MRAM has begun to be used as embedded memory in microcontrollers to replace traditional flash memory due to its endurance and low power consumption.
The main challenges for MRAM are its relatively high production cost and difficulty scaling compared to mainstream memory types. STT-MRAM technology suffers from high switching currents that cause heating and limit cell density. There is a risk of spontaneous magnetization reversal under strong external magnetic fields and radiation, as well as the problem of ensuring state stability at small technology nodes without increasing power consumption.
How MRAM works
The operating principle of MRAM is based on the tunnel magnetoresistance effect. The basic memory cell consists of a magnetic tunnel junction, which includes two ferromagnetic layers separated by a thin dielectric layer, typically magnesium oxide. One magnetic layer is the reference layer, with its magnetization fixed rigidly. The second layer, called the free layer, can change its magnetization direction under an external magnetic field or spin-polarized current. When the magnetization vectors of the free and reference layers are parallel, the junction resistance is minimal, representing a logic zero. The antiparallel state creates higher resistance, representing a logic one. For reading, a small sense current is passed through the junction to measure the resistance without destroying the stored information. Writing in modern STT-MRAM cells is done via spin-transfer torque: a higher density current is passed through the structure, which becomes spin-polarized after passing through the reference layer. This spin-polarized electron stream interacts with the magnetic moment of the free layer, causing it to change orientation according to the current direction. This switching mechanism eliminates the need for external magnetic fields, allowing denser and more energy efficient memory arrays on a chip.
MRAM functionality
- Magnetic tunnel junction as a memory element. The core function of MRAM relies on a magnetic tunnel junction consisting of two ferromagnetic layers separated by a dielectric barrier. One layer has fixed magnetization, while the magnetization direction of the second, free layer can change, encoding the logic state.
- Physical principle of data storage. Data retention is provided by the relative orientation of the magnetization vectors of the free and reference layers. If the vectors are parallel, the junction is in a low resistance state. The antiparallel configuration corresponds to a high resistance state, representing the opposite logic level in a non-destructive manner.
- Tunnel magnetoresistance effect. The read function is based on the tunnel magnetoresistance effect. The magnitude of this effect quantifies the difference in electrical resistance between the parallel and antiparallel states. A high resistance ratio is critical for reliable and fast detection of the logic state of the memory cell.
- Spin-transfer torque writing mechanism. Spin-transfer torque technology implements the switching function of the free layer. Passing a current through the magnetic tunnel junction causes it to become spin-polarized. This current generates a torque that acts directly on the free layer magnetization, eliminating the need for external magnetic fields to write data.
- 1T-1MTJ cell control scheme. To address an individual memory element, a circuit consisting of one transistor and one magnetic tunnel junction is used. The transistor acts as a switch gating access to the junction. This architecture allows precise selection of a specific cell in the array for read or write operations.
- Read process and energy efficiency. Reading the cell state is done by applying a small bias voltage to the selected junction through the open transistor. The resulting tunnel current is measured by a sense amplifier. The magnitude of the current directly correlates with the junction resistance, which is identified as logic 1 or 0.
- Non-volatile storage function. A key functional characteristic of MRAM is its ability to retain stored information for long periods after complete power shutdown. The magnetic nature of data storage provides this non-volatility, fundamentally distinguishing this technology from traditional semiconductor memories based on charge storage.
- Resistance to tunnel barrier degradation. During writing, the spin-polarized current flows directly through the thin dielectric barrier. This risks gradual degradation and breakdown. This phenomenon imposes fundamental limits on the memory cell cycling endurance, requiring optimization of current density and electrode materials.
- Separation of read and write paths function. An alternative three-terminal cell configuration using spin-orbit torque physically separates the current paths for read and write operations. In this architecture, the write current passes through an underlying conductive line, while the read current flows vertically through the junction itself. This protects the oxide barrier from degradation.
- Spin-orbit torque generation. In a three-terminal structure, magnetization switching is achieved via spin-orbit torque. This torque is generated when current flows in the plane of an underlying metallic line with strong spin-orbit coupling. The result is a transverse spin current that acts on the interface with the free layer.
- Voltage controlled anisotropy. An auxiliary switching function is implemented through the voltage controlled magnetic anisotropy effect. Applying an electric field to the junction changes the electron density at the interface. This temporarily modifies the perpendicular magnetic anisotropy of the free layer, lowering the energy barrier for its magnetization reversal.
- Selective thermal stability reduction. To achieve selective writing in an array, the above mentioned barrier reduction is used. A voltage is applied to the selected cell, reducing its coercivity. Simultaneously, the applied spin-orbit torque current switches only that cell whose thermal stability was temporarily lowered by the electric field.
- Voltage drop problem on shared lines. When multiple junctions are placed on a shared spin-orbit torque conductive line, a parasitic voltage drop occurs. This effect causes uneven potential delivery to cells located at different distances from the driver, worsening as the number of elements grows and limiting their maximum count.
- Optimization of spin-orbit torque channel thickness. The resistance of the conductive line directly depends on its thickness. Increasing thickness reduces parasitic voltage drop but simultaneously reduces current density for the same applied voltage. This trade-off requires precise calculation to minimize total write energy while maintaining functionality.
- Two-cycle write scheme for group operations. To write an array of data on a shared spin-orbit torque line, a two-cycle procedure is used. In the first cycle, all target cells are written to logic 1. Then the current direction in the line is reversed, and in the second cycle, bits with value 0 are selectively programmed.
- Suppression of read and write errors. To ensure data integrity under conditions of thermal instability and process variability, error correction codes are used. Error-correcting coding algorithms such as Hamming codes allow detection and correction of single bit errors resulting from random switching or cell parameter fluctuations.
- Sense amplifier circuitry. Reliable detection of the small magnetoresistance signal is provided by specialized amplifiers. A circuit based on charging and discharging a capacitive load through reference and measurement paths creates a differential signal. This approach reduces energy consumption per read bit by an order of magnitude.
- Operation under radiation exposure. The magnetic nature of data storage gives the MRAM cell inherent radiation hardness. Unlike transistor-based latch circuits, a magnetic bit is not subject to switching under the effect of heavy charged particles in static mode, which is critical for avionics and space applications.
- Switching current scaling. As technology nodes and junction dimensions shrink, the current required to switch the free layer also decreases. This dependence is fundamentally important for moving to denser chip layouts. The thermal stability parameter must remain sufficiently high to ensure the required data retention time.
- Read disturb suppression. When reading the same cell repeatedly, there is a non-zero probability of unintentionally switching its state with the read current. Methods to counter this effect include limiting read voltage and using data refresh schemes after a specified number of read cycles without write operations.
Comparisons
- MRAM vs SRAM. Magnetoresistive memory, like static memory, is de facto non-volatile, but unlike SRAM it does not lose data on power loss thanks to storing the bit in a magnetic tunnel junction. While SRAM is faster (nanoseconds vs tens of nanoseconds for MRAM), the latter offers significantly higher layout density because the one-transistor MRAM cell is more compact than the classic six-transistor static memory cell.
- SRAM (Fast volatile random storage of bits)
- MRAM vs DRAM. The key advantage of magnetoresistive memory over dynamic memory is true non-volatility, eliminating the need for charge refresh cycles which consume energy in DRAM. If DRAM requires constant capacitor refreshing, MRAM stores information indefinitely with no standby current draw, radically reducing storage system idle power consumption and preventing loss of critical data during sudden power failure.
- DRAM (Storage and Byte-addressing of Data)
- MRAM vs Flash NAND. Compared to NAND flash memory, MRAM technology offers orders of magnitude higher speed and virtually unlimited rewrite endurance (over 10^12 cycles), while NAND degrades after thousands of erasures. However, the key limitation of MRAM remains significantly lower storage density and consequently high cost per gigabyte, so it cannot compete with NAND in high capacity mass storage solid-state drives.
- Flash NAND (Data storage in a transistor floating gate)
- MRAM vs FeRAM. Both memories are non-volatile but differ in switching physics. In ferroelectric memory (FeRAM), writing is based on crystal polarization, leading to destructive read and limited cycle count, whereas MRAM uses spin-transfer torque with non-destructive read of junction resistance. This gives magnetoresistive memory an advantage in endurance, especially in tasks with intensive rewriting where material fatigue in FeRAM becomes critical.
- FeRAM (Ferroelectric capacitor-based Non-Volatile memory)
- MRAM vs eFlash. Embedded MRAM advantageously differs from integrated flash memory (eFlash) by compatibility with CMOS processes using fewer additional masks, simplifying scaling to technology nodes below 28 nm. While scaling eFlash below this node requires complex structures with high-voltage transistors, the back-end-of-line (BEOL) placement of MRAM cells preserves chip logic performance and reduces the cost of integrating memory into next-generation microcontrollers.
OS and driver support
Operating systems interact with MRAM as non-volatile memory through standard block device interfaces like NVMe or bus drivers such as PCIe and CXL, or by using it directly via memory-mapped I/O, allowing direct access file systems (DAX) and avoiding page cache overhead.
Security
Hardware security of MRAM is implemented by creating one-time programmable cells based on magnetic tunnel junctions with controlled breakdown, forming physically unclonable functions for generating unique chip identifiers. Emergency erasure of stored encryption keys is possible by applying an external magnetic field without physically destroying the device.
Logging
In systems with MRAM, logging of critical data such as transaction journals and finite state machine states is performed via guaranteed atomic writes to dedicated non-volatile memory pools without cache flushing to disk. In case of power failure, this prevents log loss because the commit occurs directly in the main memory array.
Limitations
Key limitations are related to cell wear during cyclic switching, requiring hardware wear leveling controllers that use randomized index rotation to protect against degradation attacks, and also to the shrinking read window as technology scales due to reduced tunnel magnetoresistance and increased cell size variability.
History and development
The technology has evolved from theoretical concepts to commercialization of STT-MRAM at the 28 nm process node as a replacement for embedded flash memory. Current research is focused on implementing spin-orbit torque and voltage controlled magnetic anisotropy mechanisms to reduce switching currents for use in last-level cache.