SoC is a single chip combining the processor, graphics, memory and input-output controllers. Instead of multiple microcircuits on the board, all key systems are located on a piece of silicon, saving space and energy.
The main field of application is mobile devices: smartphones, tablets, smart watches. SoCs also form the basis of automotive driver assistance systems, onboard computers and a multitude of Internet of Things devices — from smart bulbs to industrial sensors. They are chosen wherever minimal power consumption and compact design are critical.
Due to the high density of components, heat dissipation becomes a complex task — overheating reduces the clock frequency. Modernization is impossible: you cannot replace only the graphics core or the processor. If one module fails, the entire chip has to be replaced. Also, peripheral interfaces are fixed at the design stage and cannot be expanded after production.
How an SoC works
An SoC functions as a specialized computing system on a single substrate. The central processor executes the main instructions, while the graphics accelerator handles visualization. The digital signal processor is responsible for audio and video, while specialized accelerators (for example, an NPU for artificial intelligence) take on repetitive machine learning tasks. All blocks exchange data via an internal high-speed bus, obeying a single memory controller, which eliminates the bottlenecks typical of separate components on a motherboard. Unlike the classical chipset architecture, where the north and south bridges are physically separated, an SoC integrates them on a single die, and compared to modular systems (SOM), it does not use a printed circuit board for unification — all connections are made directly in the silicon. This brings the SoC closer to microcontrollers, but unlike the latter, it is capable of running full-fledged operating systems such as Linux or Android and operates with orders of magnitude greater computational resources, while remaining a complete device, not just a processor.
SoC functionality
- Integration of processor cores. The central processor in an SoC is implemented as one or multiple cores with ARM, RISC-V or x86 architecture, united by a common coherent bus. Heterogeneous big.LITTLE layout combines high-performance and energy-efficient cores for dynamic load distribution and leakage minimization during idle time.
- RISC-V (Open modular instruction set architecture)ARM (Energy efficient execution of processor instructions)x86 (Execution of instructions based on CISC architecture)
- Graphics accelerator subsystem. The integrated GPU provides hardware acceleration of 3D graphics rendering and pixel processing. The block contains geometry engines, shader pipelines and texture units working with a dedicated bank of high-speed GDDR memory or a shared LPDDR pool without accessing the external bus.
- LPDDR (Low power memory)
- Memory controller. The DRAM interface implements arbitration of requests from all master devices of the die, rank management and DQ/DQS line calibration. The subsystem minimizes access latency via a multi-level system cache, uses prefetching and regulates the supply voltage for LPDDR5X standards.
- DRAM (Storage and Byte-addressing of Data)
- Digital signal processor. DSP cores perform vector multiply-accumulate operations on fixed-point data streams. Hardware accelerators process audio codecs, echo cancellation and voice triggers with low latency, allowing the central processor to transition to an energy-saving standby mode.
- Modem subsystem and radio path. The integrated modem converts the bitstream into analog quadrature I/Q signals. The path includes DAC/ADC, a phase-locked loop, power amplifiers and low-noise stages. Implementing the 5G NR protocol stack requires a dedicated control processor with strict timing.
- Neural network accelerator block. The NPU implements a systolic array of multipliers for convolutional and fully connected layers. Hardware support for quantized INT8/FP16 formats allows executing inference of computer vision and natural language processing models with performance of tens of TOPS without thermal throttling.
- TOPS (Measuring peak performance of AI accelerators)FP16 (Compact representation of Floating-Point numbers)
- Multimedia encoding pipeline. Hardware encoders and decoders work with HEVC, AV1 and VP9 formats on fixed function blocks. The pipeline implements intra-frame prediction, motion compensation and entropy compression, without consuming CPU resources and reducing power consumption during 8K video recording.
- HEVC (Effective video compression with minimal losses)AV1 (Video codec for streaming)
- Image signal processor. The ISP receives a raw stream from a Bayer format camera matrix, performing black level correction, noise reduction, demosaicing and tonal compression. Multi-frame HDR stacking operates on hardware pipelines, delivering the resulting frame before the intervention of the main processor.
- Secure enclave and crypto core. The isolated trusted execution environment (TEE) includes a hardware true random number generator, secure non-volatile memory for keys and AES/SHA accelerators. The block guarantees secure boot, storage of biometric templates and verification of digital signatures outside the insecure OS.
- Interconnects and network-on-chip. The Network-on-Chip switching fabric connects IP blocks via packet routers, supporting multiple virtual channels to prevent Head-of-Line blocking. AXI protocols ensure transactions with guaranteed bandwidth and quality of service for streaming traffic.
- Peripheral input-output controllers. The physical layer implements support for USB 3.2 with DisplayPort multiplexing, PCI Express interfaces with lane aggregation, general-purpose input-output ports with configurable function multiplexing and system wake-up by signal level in deep sleep.
- DisplayPort (High-speed video and audio transmission)
- Sensor hub. An ultra-low-power coprocessor constantly polls accelerometers, gyroscopes and magnetometers. Fusion of inertial sensor data on a dedicated core allows tracking steps and orientation in space without waking the energy-intensive application cluster.
- Power management system. The on-die PMU manages dynamic voltage and frequency scaling for individual power domains, switching between state retention modes and complete power-down of inactive blocks. Finite state machines control the power-up sequence, eliminating current surges.
- Multi-port memory subsystem. The flash memory controller manages eMMC/UFS cell wear through a command queue with reordering. The direct memory access block scatters data across NVMe channels, supporting submission/completion queue pairs with a depth of hundreds of transactions to squeeze out full bandwidth.
- Clock generator and PLL. The clock distribution architecture is built on fractional frequency synthesizers with spread spectrum for reducing electromagnetic interference. Programmable dividers form independent frequency grids for the DRAM bus, display pixel clocks and high-speed SerDes transceivers.
- Display output controller. The composition engine overlays layers in windows, performing gamma correction and scaling. MIPI DSI or DisplayPort transmitters form differential packets, managing the hot-plug protocol and link training for outputting frames with variable refresh rate.
- Audio subsystem. The audio hub routes I2S/TDM streams between the modem, Bluetooth controller and speakers. Hardware mixers perform sample rate conversion and summation without copying data through main memory, ensuring synchronous delivery of samples with microsecond precision.
- Debug infrastructure. The built-in CoreSight tracer stores the stream of instruction and data execution in a high-speed buffer. The statistical profiling mode samples the program counter without stopping the core, identifying hot spots in the code with minimal interference in the system operation.
- Hardware virtualization scheduler. The interrupt controller with virtualization support directly delivers signals to guest OSes without exiting to the hypervisor. The IOMMU with two-level address translation isolates direct memory accesses of hardware accelerators, limiting the impact of a single virtual node failure.
- IOMMU (Isolation of direct memory access addresses)
- Short-range wireless subsystems. The integrated Bluetooth Low Energy controller performs connection establishment and GATT profiles without loading the main core. Interaction with the Wi-Fi chip is conducted via a dedicated interface, synchronizing time slots for coexistence without mutual collisions.
Comparisons
- SoC vs MCU. The microcontroller is optimized for deterministic real-time control with minimal power consumption, having a small amount of embedded memory. The SoC, in contrast, represents a heterogeneous system with powerful processor cores, a graphics accelerator and external DRAM controllers, oriented towards multitasking and processing complex user interfaces or multimedia.
- SoC vs CPU. The central processor is a discrete functional block requiring an external chipset for communication with peripherals. The SoC integrates CPU cores, GPU, neural coprocessors, memory and input-output controllers on a single die, achieving significantly higher packaging density and reducing delays in data exchange between subsystems in mobile devices.
- SoC vs FPGA. The field-programmable gate array offers a reconfigurable hardware architecture, changeable at the logic element level after production. The SoC uses fixed, hard logic, ensuring maximum clock frequency and energy efficiency. The combination of these features in heterogeneous platforms allows moving algorithms with dynamically changing standards onto FPGA fabric, and stable interfaces onto SoC cores.
- SoC vs SiP. System-in-Package combines several heterogeneous dies in one enclosure via a substrate, whereas the SoC implements all functionality on a monolithic piece of silicon. SiP wins in speed to market and the ability to mix process technologies for memory and logic, but the SoC demonstrates superiority in internal bus bandwidth and thermal resistance due to the absence of inter-die connections.
- SoC vs ASIC. An application-specific integrated circuit is designed to perform strictly one task with energy efficiency unattainable for universal solutions. The SoC is a compromise, combining programmable processor blocks with hardware accelerators. This gives engineers the flexibility to update algorithms without respinning silicon, which is critically important with frequently changing video coding standards or communication protocols.
OS and driver support
Operating system functioning on an SoC is provided through a board support package (BSP), which includes low-level code for initializing processor cores, the interrupt controller and timers, while drivers for embedded peripherals (USB, GPU, ISP) are implemented by directly mapping control registers into kernel memory and configuring direct memory access (DMA) channels for data exchange without overhead on the central processor.
Security
Isolation and access control on the chip are implemented through dividing resources into secure and normal execution worlds using TrustZone extensions for the ARM architecture, where the hardware state monitor allows context switching only through a strictly defined secure monitor call instruction, and access control is carried out at the physical address level via the memory controller, blocking unauthorized transactions from non-secure master blocks.
Logging
Low-level diagnostics are provided by built-in trace macrocells in the processor core and system bus, which form data streams about instruction execution and transfers over interconnects, multiplexed through a high-bandwidth debug port to an external analyzer without stopping the system core.
Evolution
The development of System-on-Chip technology followed the path of vertical integration of discrete components on a single die: starting with combining a processor core and input-output controllers, manufacturers moved to including analog radio frequency blocks and sensors, which led to the emergence of a heterogeneous architecture with clusters of cores of different performance, exchanging data through a coherent interconnect fabric on the chip.