Category: CPU, GPU, SoC
- NPU (Specialized processor for parallel tensor computations)
- OLED (Converting electricity into light with organic pixels)
- DisplayPort (High-speed video and audio transmission)
- AV1 (Video codec for streaming)
- HEVC (Effective video compression with minimal losses)
- AVC (Video compression with motion prediction)
- CUDA (Parallel computing on the graphics processing unit)
- VRR (Syncing display refresh rate with frames)
- FreeSync (Dynamic synchronization of monitor and graphics card frames)
- G-Sync (Dynamic synchronization of monitor and GPU frames)
- FSR (Spatial scaling with detail reconstruction)
- RT Core (Hardware accelerated ray tracing)
- Tensor Core (Hardware matrix multiplication with accumulation)
- CUDA Core (Performing parallel floating point computations)
- VRAM (High-speed buffer for graphical data)
- TDP (Project processor heat dissipation limit)
- AES-NI (Hardware acceleration of symmetric AES encryption)
- AVX-512 (Processing 16 numbers per instruction)
- AVX2 (Simultaneous processing of eight 32-bit integers)
- AVX (SIMD data processing with 256/512-bit registers)
- SSE (Simultaneous processing of multiple data with a single instruction)
- MMX (Single-cycle processing of packed integer data)
- TLB (Translation Lookaside Buffer)
- SMT (Hardware emulation of two logical processors)
- IPC (Instructions per cycle)
- TFLOPS (Computational performance meter)
- FP16 (Compact representation of Floating-Point numbers)
- TF32 (Hybrid format for accelerating tensor computations)
- Peer2Peer (Direct memory access between GPUs)
- XGMI (AMD high-speed coherent Inter-Die bus)
- XeSS (Intelligent upscaling with frame reconstruction)
- LFB (Cache Line Fill Buffer)
- LSU (Execution of load and store operations)
- IFU (Instruction Fetch and Decode)
- IDU (Transforming instructions into control signals)
- ARF (Fast architectural register storage file)
- PRF (Storage of renamed microarchitectural operands)
- RAT (Eliminating false dependencies between registers)
- RS (Buffering and dynamic instruction scheduling)
- ROB (Reorder buffer for out-of-order operations)
- RSB (Return address prediction buffer)
- BTB (Prediction of the next branch instruction address)
- BPU (Branch prediction for pipeline acceleration)
- AGU (Computing effective memory addresses)
- EU (Execution of machine instructions by the processor)
- CU (Managing the execution of machine instructions of the processor)
- FPU (Hardware acceleration of floating point computations)
- ALU (Performs arithmetic and logical operations)
- ZISC (Hardware nearest match search)
- OISC (Performing computations through a single universal instruction)
- MISC (Executing commands through a single universal instruction code)
- VLIW (Parallel execution of commands without a hardware scheduler)
- RISC (Accelerated execution of simple commands by the processor)
- CISC (Executing complex operations with a single instruction)
- EPIC (Division of responsibility for execution parallelism)
- Itanium (Explicit static scheduling of parallel instructions)
- UltraSPARC (64-bit RISC microprocessor architecture with out-of-order execution)
- SPARC (Open standard RISC architecture)
- POWER10 (Multithreaded scaling with hardware AI acceleration)
- PowerPC (RISC architecture with computation optimization)
- MIPS64 (64-bit RISC architecture with fixed instruction length)
- MIPS32 (32-bit RISC architecture with fixed instruction length)
- MIPS (Simplified pipelined RISC architecture without interlocks)
- RISC-V (Open modular instruction set architecture)
- Thumb-2 (Hybrid 32 and 16-bit instruction set)
- Thumb (Compressing 32-bit ARM instructions to 16-bit)
- AArch64 (64-bit processor architecture with fixed instruction length)
- ARM (Energy efficient execution of processor instructions)
- IA-64 (Architecture of explicitly parallel instruction computing EPIC)
- IA-32 (Provides execution of 32-bit computations)
- x64 (Extension of the 32-bit x86 architecture to 64 bits)
- x86 (Execution of instructions based on CISC architecture)