APU is a processor that combines central and graphics processors on a single die. They use shared RAM and a data bus, eliminating the need for separate slow data transfer between components, which speeds up parallel computing.
Accelerated processors are widely used in laptops, compact desktop systems without a discrete graphics card, thin clients, and gaming consoles such as PlayStation and Xbox. They are in demand in industrial single-board computers and automotive multimedia systems where physical space and power consumption are strictly limited but confident graphics and computing power are required.
A typical problem is the acute dependence of graphics core performance on RAM bandwidth, forcing the use of expensive high-frequency modules to unlock potential. Overheating of the compact die area under simultaneous load on both blocks causes throttling. An engineering challenge also lies in uneven power distribution and the inability to upgrade the graphics part without replacing the entire processor.
How an APU works
The operating principle is built on heterogeneous system architecture, blurring the boundaries between a classic processor and a coprocessor. Unlike the CPU plus discrete graphics card scheme where data is copied from system memory to video memory via the PCI Express bus, here both computing blocks have direct access to a unified address space through a shared memory controller. The processor part handles sequential tasks and logic branching, while the graphics part handles thousands of parallel threads processing geometry, physics, or machine learning algorithms. The heterogeneous task distribution mechanism allows cores to freely exchange data pointers without copying overhead. Compared to previous-generation integrated graphics that was a passive output device, an accelerated processor uses the GPU as a full-fledged vector coprocessor. At the same time, unlike mobile-class systems-on-chip, the emphasis here is on architectural integrity without moving the southbridge, maintaining x86 compatibility and power balance at the L2 cache level to reduce latencies during inter-core interaction.
APU functionality
- Heterogeneous system architecture. CPU and GPU compute cores are placed on a single die, which eliminates the physical discreteness of the PCIe bus and implements direct interaction through a common memory controller.
- Unified address space. x86 processor cores and graphics engines operate with the same virtual and physical addresses without buffer translation, eliminating software overhead on data copying between separate memory pools.
- Cache coherence between CPU and GPU. The APU hardware logic supports a full coherence protocol, usually MOESI or a derivative, allowing graphics cores to atomically read processor-modified data directly from L2 cache without flushing to DRAM.
- DRAM (Storage and Byte-addressing of Data)
- Integrated UMC memory controller. A common multi-channel DDR4/DDR5 controller serves requests from the computing and graphics domains, balancing bandwidth through traffic prioritization of the real-time display subsystem and low-latency CPU requests.
- DDR5 (High-speed energy-efficient computer RAM)DDR4 (High-speed synchronous data transfer)
- Radeon graphics core on chip. The integrated GPU contains an array of Compute Units based on GCN or RDNA architecture, equipped with asynchronous compute engine blocks, geometry processors, and raster operation blocks for processing graphics and compute pipelines.
- Hardware video encoding acceleration. The VCN or legacy VCE/UVD block provides fixed-function encoding of H.264, HEVC, and AV1 codecs without loading shader arrays, achieving low power consumption during video stream recording or broadcasting.
- HEVC (Effective video compression with minimal losses)AV1 (Video codec for streaming)
- Video stream decoding. A specialized ASIC block performs bitstream parsing, entropy decoding, and inverse discrete cosine transform in hardware, offloading stream processors and minimizing jitter during ultra-high resolution content playback.
- HSA heterogeneous programming support. The APU implements HSA Foundation specifications, defining shared page tables for CPU and GPU with memory error handling, passing pointers instead of data, and allowing GPU cores to make system calls through a local software interface.
- Infinity Fabric on-chip architecture. Internal switching of CPU chiplet, GPU, and I/O controller domains is implemented through a scalable Infinity Fabric bus, providing coherent traffic with low latency and configurable interconnect clock frequency.
- Multithreading and SMT. x86 cores use simultaneous multithreading, executing instructions of two logical threads on one physical core to fill pipeline stalls caused by cache misses and data dependencies without resource conflict with the GPU.
- SMT (Hardware emulation of two logical processors)
- APU power management unit. The System Management Unit microcontrollers dynamically scale voltage and frequencies of separate CPU and GPU domains based on current sensors, temperature, and current load from the power consumption prediction module.
- Power Gating energy efficiency technology. Unused die areas, including individual GPU Compute Units or core clusters, are completely de-energized by hardware power switches, reducing leakage currents to zero in deep sleep states without saving context in registers.
- PCI Express system bus interface. The integrated root complex outputs PCIe 4.0/5.0 lanes directly from the die for connection to a discrete accelerator or NVMe drive, eliminating additional chipset bridge latency in critical transactions.
- Hardware support for image output standards. The display pipeline contains pixel stream multiplexers, DisplayPort 2.0 and HDMI 2.1 timing controllers, as well as a DSC stream compression block for outputting an uncompressed 8K signal without external signal converters.
- DisplayPort (High-speed video and audio transmission)
- Parallel command execution queues. The graphics subsystem contains multiple hardware queues for independent compute and graphics primitive streams, allowing the asynchronous shader mechanism to simultaneously execute physics simulation and frame compositing.
- AMD TrueAudio sound processing technology. The Tensilica HiFi EP DSP coprocessor located on the APU die performs spatial audio stream processing using binaural transfer functions without occupying the resources of the main CPU arithmetic logic units.
- Platform Security cryptographic coprocessors. The ARM Cortex-A5 hardware processor manages secure UEFI boot, isolates DRAM memory encryption keys, and validates executable code signatures before x86 core initialization, protecting hypervisor space.
- ARM (Energy efficient execution of processor instructions)
- GPU memory management unit. The system I/O memory management unit serves requests from on-chip clients and PCIe, translating device virtual addresses into physical ones and isolating virtual machine address spaces for SR-IOV.
- SR-IOV (Hardware-level input-output device virtualization)
- Ray Accelerator ray tracing interface. Starting with RDNA 2 architecture, the integrated APU includes fixed blocks for BVH tree traversal and ray intersection testing with bounding boxes, reducing shader costs for highly realistic global illumination calculation.
Comparisons
- APU vs CPU plus discrete graphics card. An APU combines central and graphics processors on a single die with a unified power subsystem, whereas a CPU and discrete graphics card combination is physically separated and uses the PCIe bus. This gives the APU a win in energy efficiency and compactness but limits the thermal package and graphics performance by the amount of shared RAM.
- APU vs CPU with Intel integrated graphics. The fundamental difference lies in architecture: the APU uses a modular heterogeneous system architecture for direct GPU access to memory, whereas classic Intel solutions long used a split memory controller. This provides the APU with higher bandwidth in parallel computing and superiority in resource-intensive graphics tasks without a discrete adapter.
- APU vs SoC. A system-on-chip integrates all components including I/O controllers, memory, and radio modules on a single silicon base. Unlike an SoC, an APU focuses exclusively on the synergy of computing cores and powerful graphics, requiring an external chipset. Therefore, an APU is used in desktop systems with upgrade potential, while an SoC dominates in ultra-mobile devices with rigid board layout.
- SoC (Integration of all computer components on a single chip)
- APU vs GPGPU. A general-purpose graphics processor uses the massively parallel architecture of a video card for non-graphics calculations via CUDA or OpenCL. An APU minimizes data copy latencies between separate CPU and GPU memory thanks to a physically unified address space. Such heterogeneous unification is critically important for tasks where data is intensively processed and visualized in real time.
- CUDA (Parallel computing on the graphics processing unit)
- APU vs FPGA. A field-programmable gate array offers reconfigurable hardware logic, achieving maximum efficiency on specific algorithms at the cost of programming complexity. An APU, on the contrary, operates on a fixed x86 architecture with a universal instruction set. The choice between them defines the priority: an APU gives ease of development under standard APIs, while an FPGA gives deterministic ultra-low latency in stream data processing.
Architectural integration of CPU and GPU
In an APU, the central and graphics processors are placed on a single die and connected to a unified bus, allowing them to use shared RAM without data copying via the PCI Express bus. This is implemented through a hardware Unified Memory Controller block and heterogeneous Unified Memory Access technology, where both computing units see one address space.
OS and driver support
The operating system identifies the APU as a single device with two classes of execution cores through ACPI tables and Heterogeneous System Architecture interfaces. Drivers include the AMD Software package for Windows, where the Adrenalin graphics driver manages GPU command queues and the hardware scheduler, and in Linux environments, amdgpu kernel components and Mesa for OpenGL/Vulkan provide access to shared buffers and synchronization via fencing without redundant copying.
Security and isolation
In an APU, security functions are provided by the built-in AMD Platform Security Processor based on an ARM core, which launches before the main firmware, checks UEFI integrity through a chain of trust using hardware keys stored in eFuse memory, and creates isolated execution areas for trusted applications through AMD Secure Encrypted Virtualization hardware virtualization.
Logging and telemetry
The APU driver and microcode generate hardware events logged through Event Tracing for Windows or sysfs/debugfs in Linux, where the amdgpu module records the state of command queues, timeouts, GPU resets, and the embedded system platform controller captures APU power consumption on VDDCR_SOC rails using an integrated analog-to-digital converter and stores these values in the system event log via BIOS.
Limitations and evolution
The main physical limitation of APUs remains the bandwidth of shared DDR memory, which is inferior to the bandwidth of discrete GDDR video memory. To compensate, large Infinity Cache caches on the die have been introduced. Development has progressed from the first Llano with separate memory blocks through Heterogeneous Uniform Memory Access technology in Kaveri to modern chiplet-based APUs with a dedicated I/O die and an active Infinity Fabric bridge that ensures cache coherence between compute chiplets without non-uniform access penalties.