GDDR7 is the newest type of video memory operating on PAM3 signaling technology. Unlike its predecessors, it transmits three bits per two clock cycles instead of two bits. This enables a sharp increase in bandwidth without a significant rise in frequency, reducing energy consumption per transmitted bit of information.
Description
| Simple description | Imagine a racetrack where instead of one narrow lane for trucks, twice as many lanes are laid for sport motorcycles. Data is delivered from memory to the processor twice as fast, but using less fuel and without overheating. |
| Medium complexity description | A new video memory standard using PAM3 signaling instead of NRZ/PAM4. This allows raising the data transfer rate per pin to 32–40 Gbps while maintaining energy efficiency. The chip can operate in independent sub-channels, increasing request processing parallelism and reducing latency. |
| Technical description | Synchronous dynamic random-access memory based on DRAM cells, compliant with the JESD250 specification. It uses multi-level pulse amplitude modulation (3-level, PAM3) with 1.5 bits per clock cycle. The chip architecture is divided into 4 independent channels (x32) with a doubled number of banks. Includes Eye-Max mode and linearly distributed error correction (ODECC) for integrity at high frequencies. |
Technical Features
| Top-level category | Memory | Developer/author | JEDEC (JC-42 Committee) |
| Subcategory | Graphics DRAM (SGRAM) | Standardizing body | JEDEC |
| Application domain | Graphics accelerators, HPC, AI accelerators, Game consoles | Standard number | JESD250 (GDDR7 SGRAM) |
| Predecessor | GDDR6 / GDDR6X | Entity type | Hardware memory interface standard |
| Bandwidth | Up to 160 GB/s (per chip, 40 Gbps per pin) | Clock frequency | Up to 20 GHz (GDDR7-effective) |
| Power consumption | Reduced by 20-25% compared to GDDR6 at the same speed | Supply voltage | 1.2 V (VDD) / 1.8 V (VDDQ) (typical) |
| Width/block size | x32 (four independent 8-bit sub-channels) / 16 banks | Error correction mechanism | ODECC (On-Die ECC) with real-time modes |
| Interaction model | Point-to-point connection (P2P) controller-memory | Signaling | PAM3 (3-level pulse amplitude modulation) |
| Backward compatibility | Physically and logically incompatible with GDDR6/6X | Forward compatibility | Not provided |
| Form factor | BGA package (ball grid array) standard 180-ball | Number of contacts/pins | 266 (standard package) |
| Process node (nm) | 10 nm class (DRAM cells) | Major vendors | Samsung, Micron, SK Hynix |
Advantages and Limitations
| Advantages | Limitations |
| Significantly higher bandwidth per chip and per watt compared to GDDR6, which is critical for 4K gaming and ray tracing. PAM3 technology delivers a clean signal without overheating. | Requires development of entirely new GPU chips and PCB designs, as it is electrically and physically incompatible with GDDR6. At launch, higher chip cost and lower availability compared to the mature predecessor. |
Application Areas
| Product | Application area |
| Next-generation graphics cards (expected in NVIDIA GeForce RTX 50 series, AMD Radeon RX 8000 series), industrial computing units for machine learning | High-performance desktop and mobile graphics cards for gamers, professional visualization (CAD/CAM), neural network training and inference, future game consoles. |