NAND Flash is non-volatile memory that retains information without power. Imagine an array of cells, each trapping electrons in an isolated pocket. The presence or absence of this charge determines a logical zero or one. Unlike a hard disk drive, there are no moving parts, and data is read by measuring the threshold voltage on a specialized transistor.
This technology is the foundation of solid-state drives, USB flash drives, microSD cards, as well as the built-in storage in smartphones, tablets, ultrabooks, and gaming consoles. It is used in server storage where high random access speed and low power consumption are important. NAND chips are installed in industrial single-board computers, automotive infotainment systems, IoT sensors, and storage modules in aerospace vehicles.
Typical problems
The main limiting factor is cell wear. Each program and erase cycle damages the floating gate insulator, causing charge leakage and data corruption. When a cell reaches its maximum number of rewrite cycles, it can no longer reliably switch. Interference occurs between adjacent cells due to parasitic capacitive coupling. Multi-level structures become sensitive to temperature fluctuations and background noise. To combat degradation, redundancy, error correction, and wear leveling are employed.
Operating principle
The basis of NAND memory is a structure of floating gate transistors connected in series into strings. Each such transistor has a control gate and an isolated polysilicon layer surrounded by a dielectric. Data is written using Fowler-Nordheim tunneling: a high positive voltage is applied to the control gate, creating a strong electric field. Electrons from the channel overcome the thin oxide layer and accumulate in the floating gate, raising the cell’s threshold voltage. This fixes the logical value.
Erasing works in reverse: a high positive voltage is applied to the substrate while the control gate is grounded. Electrons leave the floating gate, returning the threshold voltage to its initial state. The NAND architecture organizes cells into pages and blocks. Reading and programming are performed at the page level, while erasing is only possible for entire blocks. This approach simplifies array circuitry but creates limitations when modifying arbitrary data: before writing to a partially filled block, the entire block must be erased and the information redistributed.
To increase storage density, multi-level cells capable of distinguishing four, eight, or sixteen charge levels are used. This doubles, triples, or quadruples capacity per transistor but tightens the requirements for analog voltage measurement precision. The memory controller manages complex algorithms: soft-decision error correction coding, wear monitoring, and dynamic data movement to evenly distribute cell wear across the entire array.
Functionality
- Hierarchical memory organization. NAND Flash has a strict hierarchy: a die is divided into planes, which consist of blocks, and those in turn consist of pages. This structure defines access logic and the limitations on write and erase operations, enabling efficient management of large data volumes.
- Page-based read and write addressing. Read and program operations in NAND Flash are performed at the page level. Typical page size ranges from 4 to 16 KB. This means it is impossible to rewrite a single byte within a page without erasing the entire block, a fundamental architecture limitation.
- Block-oriented erasure. Data erasure, unlike reading and writing, is performed only on a block basis. A block typically contains 64 to 128 pages. Before writing new data to a page, the entire block containing it must be erased, necessitating background garbage collection in SSDs.
- Floating gate cell architecture. The memory cell is based on a transistor with a floating gate that is electrically isolated from the rest of the structure. Charge injected onto this gate changes the transistor’s threshold voltage, which determines the cell’s logical state. Charge retention guarantees the memory’s non-volatility.
- Charge trap cell technology. An alternative to the floating gate is charge trap technology. Here, charge carriers are stored in discrete trapping centers within a non-conductive silicon nitride layer. This improves resistance to local defects in the tunnel oxide and reduces interference between adjacent cells during scaling.
- Multi-level cell states. To increase storage density, multi-level cells are used. MLC, TLC, and QLC technologies store 2, 3, and 4 bits per cell respectively. This is achieved by dividing the threshold voltage range into many levels, which imposes stricter requirements on charge control precision and noise immunity.
- ISPP programming method. To precisely control threshold voltage, Incremental Step Pulse Programming (ISPP) is used. Voltage pulses with increasing amplitude are sequentially applied to the cell gate, with state verification performed between pulses. The process repeats until the cell reaches the required charge level.
- Read function using reference voltages. Data is read by applying a set of reference voltages to the cell’s control gate and determining its conductivity. For multi-level cells, sequential comparison with multiple thresholds is used to classify the stored state. Accurate setting of these voltages is critically important to minimize errors.
- Plane-level parallelism. NAND chips support simultaneous operations on different planes (multi-plane operations). Read, write, or erase commands can be sent to multiple planes within a single die, significantly increasing throughput through parallelization.
- Copyback hardware core. To optimize garbage collection and data migration within the die, the Copyback function is used. Data is read from one page into the plane’s buffer register and then immediately programmed into another page of the same plane without external transfer to the controller.
- Internal read with move operation. An advanced data copying variant, SuperCopyback, solves the problem of intra-page fragmentation. It allows multiple reads and a single write at the superblock level, enabling sub-page level data migration without throughput loss and while preserving RAID redundancy.
- Error Correction Code (ECC) mechanism. To ensure data integrity, error-correcting codes such as BCH and LDPC are used. The controller computes and stores codewords during writing, then decodes them during reading to detect and correct bit errors caused by charge degradation in cells.
- Soft-decision LDPC decoding. Low-Density Parity-Check codes use bit value probability information. Soft decoding involves performing multiple read operations with different threshold voltages to accurately estimate log-likelihood ratios, dramatically improving correction capability compared to hard decoding.
- Data recovery via RAID. When ECC cannot correct errors, a redundancy mechanism at the superblock level (RAIN – Redundant Array of Independent NAND) is used. The controller reads all intact pages from the stripe and computes the missing data using XOR operations, serving as the last line of defense before data loss.
- Wear leveling. Due to the limited write/erase cycle life of cells, the controller redistributes requests to avoid premature degradation of some blocks while others remain idle. Logical addresses are dynamically remapped to different physical blocks, ensuring even wear distribution across the entire memory array.
- Garbage collection. Background garbage collection frees blocks occupied by obsolete pages. The process moves valid data from a partially used block to a clean one, after which the old block is erased. This operation is critical for maintaining free space but creates additional write channel load.
- Write amplification. A key performance metric for NAND storage, defining the ratio between physically written data and host requests. Garbage collection and wear leveling are primary sources of write amplification, reducing drive lifespan and requiring spare block reservation.
- SLC mode caching. To improve write performance, part of the memory in QLC or TLC mode is dynamically configured as a high-reliability SLC buffer. Data is first written quickly to this cache and then compacted in the background into multi-level cells of the main array.
- Power-fail protection programming. To prevent data corruption during sudden power loss, controllers use large capacitors or backup power supplies. The stored energy is sufficient to properly complete the current page program operation and save address translation tables.
- Read disturb protection. Repeatedly reading the same page can alter the charge of neighboring cells (read disturb). The controller firmware maintains read operation counters for each block, and when a critical threshold is reached, it initiates preventative data migration to a new block followed by erasure of the problematic one.
- Thermal throttling. Under heavy load, the temperature of NAND dies can exceed safe limits, accelerating charge leakage from cells. The management system dynamically reduces I/O operation frequency and programming speed to prevent irreversible degradation of non-volatile cells.
Comparisons
- NAND Flash vs NOR Flash. NAND Flash connects cells in series for high density and low cost per gigabyte, while NOR Flash uses parallel connection for fast random access. The main difference lies in architecture: NAND is optimized for streaming large blocks of data (video, archives), whereas NOR allows the CPU to execute code directly (XIP) without loading into RAM, which is critical for device booting.
- NAND Flash vs 3D XPoint (Intel Optane). Traditional NAND Flash writes data in pages with mandatory erasure of entire blocks, while 3D XPoint supports byte addressing and in-place overwrite without complex garbage collection. This gives Optane a radical advantage: its latency is about 10 microseconds compared to 80-100 microseconds for the best NAND drives, and its endurance is tens of times higher, bridging the gap between memory and storage.
- NAND Flash vs EEPROM. The main difference lies in operation granularity: EEPROM allows erasing and rewriting individual bytes, while NAND Flash operates on large blocks and pages. Although EEPROM has phenomenal reliability (up to 1 million rewrite cycles) and is ideal for storing settings, its capacity rarely exceeds 1 MB, whereas NAND offers terabytes of cheaper storage but requires complex controllers for wear leveling and error correction.
- NAND Flash (SSD) vs HDD (Magnetic Disks). NAND Flash in SSDs provides access time of about 0.1 ms due to the absence of moving parts, while hard disk drives (HDDs) require 5-10 ms for magnetic head positioning. Although HDDs retain a cost-per-terabyte advantage for archival storage, NAND drives are completely silent, more resistant to vibration, and capable of handling multiple random I/O operations in parallel, making them the standard for system booting and databases.
- NAND Flash vs RAM. NAND Flash is non-volatile memory that retains data for decades without power, while DRAM loses all information within fractions of a second after power-off but offers speeds orders of magnitude higher. In modern systems, DRAM serves as an ultrafast cache for active CPU processes, while NAND acts as a slow but persistent storage; when launching applications, data is always copied from slow NAND to fast RAM for smooth user operation.
- DRAM (Storage and Byte-addressing of Data)
OS and driver support
Operating systems interact with NAND Flash through a multi-level driver architecture. At the low level is the NAND Flash Controller (NFC), whose driver implements hardware-dependent functions: sending commands, addresses, and managing chip select lines. Above it operates the NAND chip layer, implementing basic operations (page read/write, block erase) according to vendor-specific commands. Since NAND does not support in-place update, a Flash Translation Layer (FTL) is introduced to emulate a block device, translating logical addresses to physical ones. At the final interface point, the OS creates character or block devices (e.g., GEOM in FreeBSD), allowing applications to read and write data using standard system calls.
Security
Security of NAND storage is implemented through a combination of hardware data protection, cryptography, and strict access control. Modern SSDs use on-the-fly encryption and secure erase functions that physically erase blocks or cryptographically wipe encryption keys. User data integrity is ensured by Error Correction Codes (ECC), which compute redundant codes (often for a 512-byte block or sector size) and store them in a reserved area of the page, enabling detection and correction of corrupted bits during reading. In case of power failures, file systems such as UFFS guarantee operation atomicity and metadata consistency through journaling and protection against partial page writes.
Logging
Logging in flash memory leverages the nature of the memory by writing changes not over old data but sequentially into new free space (the journal), aligning with the copy-on-write principle of the FTL. When a file system commits a transaction, it writes all changes to the journal area, and then a checkpoint synchronizes these duplicates with the main storage. To combat the resulting redundancy and reduce write amplification, drivers implement duplicate block invalidation schemes via TRIM commands, informing the flash controller that old copies are no longer needed and are subject to garbage collection.
Limitations
A key physical limitation of NAND Flash is the inability to write to a non-empty cell — before programming data, a block must be completely erased. Lifespan is limited by a finite number of program/erase (P/E) cycles, during which the tunnel oxide layer wears out due to electron trapping, leading to cell degradation and data retention errors. In addition to wear, reads and writes in neighboring cells create parasitic voltage, causing the disturb effect — an unintended change in threshold voltage — which requires increasingly powerful error correction code (ECC) algorithms to maintain data reliability.
History and development
The evolution of NAND Flash began with the invention of flash memory at Toshiba in the 1980s as non-volatile memory with electrical block erasure. To increase capacity and lower cost per bit, the technology progressed from SLC (1 bit per cell) through MLC and TLC to QLC (4 bits per cell), sacrificing endurance from 100,000 to approximately 1,000 P/E cycles. The drive for further scaling led to the emergence of 3D NAND, where cells are stacked vertically, and to improve reliability in multi-level structures, floating gates have been replaced by charge traps (Charge Trap Flash), which are less susceptible to electron leakage. In parallel, controllers have evolved, implementing complex wear leveling algorithms and bad block management to maintain drive stability.