3D XPoint is a type of non-volatile memory that occupies an intermediate position between RAM and solid-state drives. To simplify, it works almost as fast as DRAM but retains data after power loss, similar to flash memory. The technology bridges the performance and latency gap between storage and memory, allowing more data to be stored closer to the processor.
The technology formed the basis of Intel Optane products, presented in several form factors. The most common is fast caching drives in consumer and enterprise systems, accelerating hard disk performance. In servers and data centers, Optane Persistent Memory modules are installed directly into DIMM slots, enabling the creation of huge arrays of non-volatile memory for databases and real-time analytics. Specialized SSDs were also produced for write-intensive workloads where low latency and high endurance are critical.
Typical problems
The main obstacle to mass adoption was the extremely high cost per gigabyte of memory, significantly exceeding the price of NAND flash. The technology required the use of only new Intel hardware platforms of a specific generation, which limited compatibility. Software needed special adaptation to effectively use byte addressing. Ultimately, high production costs and a limited market led to the winding down of the entire Intel Optane business.
How 3D XPoint works
Unlike NAND memory, which stores charge in floating-gate transistors, and DRAM, which stores charge in capacitors, 3D XPoint is based on changing the bulk properties of the material itself. The basis is a gridless crossbar structure consisting of perpendicular word lines and bit lines. At each intersection of these lines is a memory cell consisting of a selector element and a storage element. Data storage is achieved through reversible phase change in the bulk of a chalcogenide material without using transistors.
The write and read mechanism is based on applying voltages of varying magnitude and duration to the intersecting conductors. To write data, a strong electrical pulse is applied to the cell, which changes the atomic structure of the storage material: in an amorphous state, the cell has high resistance and represents a logical zero, while in a crystalline state, it has low resistance, representing a logical one. For reading, a weaker voltage pulse is applied, insufficient to change the state, and the flowing current is measured. Three-dimensional stacking is achieved by overlaying several such crossbar arrays on top of each other, which is reflected in the name 3D. Since writing does not require prior block erasure, data access occurs at the level of individual bytes, which dramatically reduces latency and increases endurance compared to NAND flash memory.
3D XPoint functionality
- Transistor-less memory cell. At the core of Optane is a cell consisting of a selector and a memory element connected in series. Unlike DRAM, data storage does not require constant charge refresh on a capacitor, and switching occurs through changes in bulk material properties, bypassing classical transistor access.
- Bulk property-based switching. The functionality is based on changing the resistivity of chalcogenide glass. When a threshold voltage is applied, a reversible phase change occurs in the bulk of the material, not just in the heated area. This distinguishes 3D XPoint from PCM, eliminating the need to melt the entire cell.
- Symmetric selector cell. The selector (OTS — Ovonic Threshold Switch) turns on when the threshold voltage is reached, providing high current for switching the memory layer. The key function is a sharp nonlinear drop in selector resistance, which effectively isolates unaddressed cells in the crossbar array without transistors.
- Cross-Point architecture. Cells are located at the intersection of perpendicular bit lines and word lines without direct contact with the semiconductor substrate. Functionally, this allows current to be sent vertically through the selected cell rather than across the transistor surface, multiply increasing packing density by eliminating parasitic elements.
- Vertical bundled via technology. Interconnects between memory layers and the logic die underneath are made through through-holes in bus bundles. This solves the scaling problem by routing signals from the dense array directly to CMOS circuits, bypassing signal spreading along horizontal traces.
- Physical separation of addressing and storage. The logic control circuitry is completely placed on a separate die under the memory array. This means that expensive high-precision lithography is used only for CMOS periphery, while memory layers are formed using simpler methods, optimizing cost without losing cell performance.
- Byte addressability. Unlike NAND, where the minimum write size is a page, 3D XPoint allows software modification of data at the bit level, effectively working byte by byte. This function is achieved through the ability to apply voltage strictly to a single line intersection without physically disturbing neighboring cells in the array.
- Direct access via DDR bus. Thanks to low latency and byte addressability, Optane modules (Apache Pass) were installed in standard DIMM slots and connected to the processor memory bus. This allowed access to the non-volatile storage through load/store instructions, bypassing the block I/O driver stack.
- Two application operating modes. The software ecosystem provided direct access (App Direct), where the volume is seen as persistent memory with a file system, and Memory Mode. In the latter, Optane became visible RAM, while DRAM acted as a hidden last-level cache, aggregating requests with minimal latency.
- Hardware cache coherency. When integrated in Memory Mode, the processor memory controller hardware tracks cache hits and misses. Requests not satisfied by the DRAM cache are redirected directly to the Optane controller at bus clock frequency, eliminating software interrupts and data copying.
- Atomic cell wear. The built-in wear leveling algorithm in the controller distributes writes evenly across physical addresses. Unlike block translators in SSDs, data movement here occurs at the row and column level of the array with very small granularity, which is critically important under workloads typical for system memory.
- In-place write without erase. In NAND flash, a bit cannot be overwritten without first erasing an entire block. Optane technology supports true in-place overwrite: the controller can change the cell state from crystalline to amorphous without an erase cycle, instantly freeing the local address for new data.
- Non-volatile context protection. Upon sudden power loss, the internal power supply reserve capacitance of the module guarantees retention of all data in the array. The absence of supercapacitors for emergency dumping, characteristic of NVDIMM-N, is ensured by the inherent nature of the medium, which stores state passively.
- Predictably low latency. The QoS (Quality of Service) quality curve is practically flat. Thanks to the deterministic nature of transistor control logic and the absence of background garbage collection, the 99.999th percentile read latency remains within microseconds and does not fluctuate by orders of magnitude during internal operations.
- Controller-level mirroring. Hardware support for two-channel interleaving by processor memory controllers allows transparent creation of fault-tolerant configurations for the OS. Upon degradation or failure of part of one module’s cells, data can be retrieved from the mirror set without activating software RAID.
- Hybrid hysteresis write. The write process uses pulses of different amplitudes and fall slopes. A short sharp fall heats the material to melting, forming a high-resistance amorphous state. A long smooth fall initiates recrystallization, returning the low-resistance state, completely eliminating thermal crosstalk for neighbors.
- Carbon-based isolation adhesion. To prevent material diffusion between word lines and bit lines under high write temperatures, a specific carbon adhesion sublayer is applied. It functions as a thermal shield, localizing heating strictly within the chalcogenide bulk and protecting metallization from degradation.
- Platform-dependent clock synchronization. The DDR-T2 interface used by Optane DIMM employs a differential signaling protocol. Functionally, it separates command and data clock frequencies, allowing the buffer on the module to recover synchronization over increased line length, reducing jitter compared to standard DDR4.
- DDR4 (High-speed synchronous data transfer)
- Built-in crypto module with key wrapping. The module controller contains a hardware AES-XTS engine with a 256-bit key. Encryption and decryption run at full line speed, while security keys never leave the chipset boundaries and are wrapped by a hardware root of trust, making physical removal of memory chips for dumping useless.
- S.M.A.R.T. log generation for non-volatile memory. Attributes such as cell wear-out percentage, temperature maxima, and volume of data moved during wear leveling are updated directly in the controller. Access to them is provided via a dedicated MCTP channel through SMBus, not consuming bandwidth of the main read/write channel.
- Pre-failure data migration. Upon detecting read instability in weak cells caused by accumulated wear, the controller proactively copies data to a spare area of the array. This read relocation process is transparent to the processor and prevents the development of uncorrectable hardware errors without stopping the command stream.
Comparisons
- 3D XPoint vs NAND Flash. Optane offers a fundamentally different physical mechanism of state switching based on bulk resistance change, whereas NAND uses charge trapping by a floating gate. This gives 3D XPoint a response time of about 10 microseconds versus ~100 microseconds for the best SSDs, and write endurance is measured in millions of cycles versus thousands for flash memory.
- 3D XPoint vs DRAM. Unlike volatile DRAM, which loses data without power, Optane provides true non-volatility with byte addressing, but with latencies in the hundreds of nanoseconds versus tens of nanoseconds for RAM. This places it in a unique Storage Class Memory class, blurring the line between memory and storage.
- 3D XPoint vs ReRAM. The technologies share a resistive principle, however Optane uses a phase change in chalcogenide glass, while ReRAM uses the formation and rupture of conductive filaments in an oxide layer. Intel’s solution demonstrates significantly higher state stability and temperature endurance, whereas ReRAM currently gravitates toward embedded memory roles due to scaling issues.
- ReRAM (Data storage through cell resistance)
- 3D XPoint vs MRAM. Magnetoresistive memory operates on electron spin and theoretically possesses infinite endurance, surpassing Optane, but suffers from low write density and sensitivity to external magnetic fields. 3D XPoint wins due to two-layer 3D stacking, providing an order of magnitude greater capacity in the same physical volume.
- MRAM (Data storage using magnetic states)
- 3D XPoint vs Optane PMem. Functionally, this is the same hardware core, but PMem operates in direct access mode via the DIMM bus with load/store instructions, bypassing the NVMe driver. This reduces latency to sub-microsecond values, making the memory truly transactional, whereas the Optane SSD form factor remains a block device with I/O stack overhead.
OS and driver support
Support for 3D XPoint under the Intel Optane brand was implemented through two operating modes: as a high-speed block storage device (NVMe SSD) and as non-volatile memory (Persistent Memory, PMem) with byte addressing via the DDR-T protocol, which required fundamentally different driver stacks. For PMem mode, the operating system used drivers conforming to ACPI specifications (NFIT tables), creating a Region abstraction that was divided into Namespaces by the ndctl driver and mounted either as a block device through the pmem driver (with DAX support — direct access bypassing page cache) or as a file system with direct access (e.g., ext4-DAX). Support was provided at the kernel level starting with Linux version 4.x and Windows Server 2019 (with the ipmctl driver for management and NTFS with DAX volumes), while standard NVMe mode did not require specific drivers beyond the OS built-in stack.
Security
Data protection on Optane drives is implemented at hardware and software levels through compliance with enterprise security standards, including hardware 256-bit AES-XTS controller encryption, where encryption keys are generated by a built-in hardware True Random Number Generator (TRNG) and never leave the chip boundaries, and access management is performed via TCG Opal 2.0 and Ruby SED (Self-Encrypting Drive). In PMem mode, security is ensured by integration with platform security mechanisms such as Intel SGX for creating isolated enclaves in memory and the Secure Erase protocol, which overwrites encryption keys in microseconds, rendering data unreadable, and all erase and reflash commands are executed only after authentication via signed firmware using asymmetric cryptography to prevent firmware attacks.
Logging
Internal logging in 3D XPoint devices is organized through non-volatile write mechanisms at the system level and built-in controller metadata structures, where Write-Ahead Logging (WAL) techniques are applied at the microcode level to guarantee atomicity of indirection table updates. In PMem mode, operation logging is implemented through Persistent Memory Development Kit (PMDK) libraries, using libpmemlog to create transaction logs directly in byte-addressable PMem regions, bypassing system cache. Log integrity during power failures is guaranteed by processor instructions (CLFLUSHOPT, CLWB, and SFENCE memory barriers) ensuring ordered flushing of data from CPU cache back to the non-volatile 3D XPoint medium.
Limitations
The fundamental limitations of 3D XPoint technology are related to the physical limits of cell density scaling compared to NAND memory, which resulted in the inability to create drives with capacities exceeding 1.5 TB per device while maintaining economic efficiency, as well as degradation of write performance at low queue depths (QD1) due to the nature of the cross-point architecture requiring pre-erase of bits before writing at the selector (OTS) level, causing a write cliff phenomenon — a sharp drop in throughput after filling the SLC-like buffer. At the system level, a limitation was the need for memory segmentation in PMem mode (available only in Memory Mode, App Direct, or mixed mode configurations) and the impossibility of hot-swapping Optane DIMM modules without a complete server shutdown, as well as high write latency relative to DRAM (around 300-400 ns versus ~100 ns), which precluded full replacement of RAM in latency-sensitive applications.
History and development
3D XPoint technology was announced in July 2015 as a result of joint development by Intel and Micron, implementing the concept of a bulk crossbar memory array with a silicon-free selector based on chalcogenide glasses and a cell based on the phase change effect in bulk, which overcame the limitations of traditional phase change memory (PCM) by impacting the atomic structure of the material in three dimensions. The first commercial product was Intel Optane Memory (2017) in M.2 format for HDD caching, followed by Optane SSD 900P/905P aimed at enthusiasts, and the culmination of development was the release of Optane Persistent Memory modules of the 100 and 200 series (Apache Pass, Barlow Pass), integrated into DIMM slots of Purley and Whitley server platforms. In 2021, Micron exited the joint venture, selling the Lehi fab to Texas Instruments, which halted the development of new generations (Platinum Pass), and in 2022 Intel announced the complete winding down of the Optane business and the write-down of assets worth 559 million dollars, ending the history of a technology that could not compete with the exponential growth of 3D NAND layers and falling DRAM prices.