FSR 4 is an AMD technology based on machine learning that increases resolution and image sharpness in games. It renders the image at a low resolution, and then a smart AI model restores details, ensuring high frame rates without noticeable loss of graphics quality.
The technology is primarily used in demanding computer games with ray tracing and high graphics settings. It is natively integrated into engines supporting DirectX 12 and Vulkan APIs, and is available exclusively on video cards with the RDNA 4 architecture (Radeon RX 9000 series). The main usage scenario is achieving smooth 60+ FPS at resolutions like 4K on high refresh rate monitors, where classic rendering falls short.
The key limitation lies in its exclusivity to the new generation of graphics processors, leaving owners of RDNA 3 without support. In scenes with fast motion and an abundance of small particles, the algorithm sometimes demonstrates instability in temporal data accumulation, leading to flickering and a smearing effect. Additionally, on aggressive performance settings, artifacts may appear as residual halos around moving objects.
How FSR 4 works
Unlike the spatial algorithms of its predecessor FSR 3.1, which operate on a single frame, FSR 4 uses a hybrid temporal approach. The core of the technology is a convolutional autoencoder with a lightweight Transformer architecture, optimized for the matrix accelerators of RDNA 4. During operation, the engine passes the current low-resolution frame, pixel motion vectors, scene depth data, and the color buffer from the previous reconstructed frame to the model. The network analyzes pixel history, predicting their displacement, and synthesizes the missing high-frequency details while suppressing noise. The fundamental difference from Nvidia DLSS 4 (Nvidia’s transformer model without convolutional elements) lies in a lighter and more energy-efficient network structure, reducing the load on tensor units but sometimes falling short in stability of fine textures in static scenes. Compared to Intel XeSS, which uses universal DP4a instructions on non-XMX cores, AMD’s solution is rigidly tied to the dedicated hardware of RDNA 4, which eliminates compromises in computation accuracy and allows frame processing in fractions of a millisecond, ensuring minimal input latency.
FSR 4 functionality
- Matrix FP8 accelerator architecture. Matrix operation acceleration units in RDNA 4 are transitioned to native FP8 computation with 2:4 sparsity. This doubles peak computational throughput compared to the previous generation’s INT8/WMMA sets without losing data representation accuracy.
- Matrix (Storing data in tabular form)
- Introduction of a transformer upscaling model. FSR 4 abandons convolutional neural networks in favor of a hybrid vision-transformer. The Efficient ViT architecture extracts features in a multi-scale attention window, effectively capturing long-range pixel dependencies critical for restoring fine geometry and textures.
- Cross-attention block with frame history. A cross-attention mechanism links the current low-resolution frame with a deformed set of pixels from the history buffer. Bidirectional optical flow estimation compensates for motion, allowing the fusion of sub-pixel information beyond the static reprojection window.
- Dynamic Ray Tracing Denoiser adjustment. The predictive part of FSR 4 contains a built-in spatio-temporal ray denoiser. The neural network visor estimates local tracing density and automatically switches the ratio of denoising to upscaling, preventing over-blurring at low ray counts.
- Explicit Anti-Lag Frame Interpolation module. A neural intermediate frame generation block without CPU involvement is integrated into the compute pipeline. Unlike driver-based solutions, interpolation is performed asynchronously after upscaling with explicit UI-layer marking to minimize parasitic input latency.
- Native Cooperative Vectors support. The driver interface is based on DirectX Cooperative Vectors, linking the game’s shader backend directly to the matrix NPU cores of the RDNA 4 architecture. This eliminates redundant compute queue dispatcher calls, embedding the neural network pass into the standard graphics command buffer.
- NPU (Specialized processor for parallel tensor computations)
- Hardware disocclusion artifact blocking. A low-power depth verification coprocessor has been added to the third Dual Issue Stream Processor. By analyzing the disparity map, it generates a disocclusion mask before network entry, preventing neural network hallucinations at the boundaries of objects that have just entered the frame.
- W4A8 weight quantization with preserved accuracy. All transformer convolutions are executed in hybrid mode – weights are quantized to 4 bits, and activations to 8 bits. A specialized hardware delta-dequantization module restores the statistical distribution on the fly, keeping the PSNR loss within 0.1 dB of a full FP16 run.
- FP16 (Compact representation of Floating-Point numbers)
- Non-uniform resolution scaling. FSR 4 is capable of asymmetrically increasing frequency along the X and Y axes. The source frame rendering is conducted in proportions different from the target display, and the network’s internal UV mapping compensates for pixel grid anisotropy without the cost of an intermediate buffer.
- Ultra-high resolution 4x reconstruction mode. The exclusive Native AA preset analyzes the frame without a downsampler. It extracts an edge curvature map and reconstructs line geometry based on a fully connected decoder model, providing the equivalent of deep learning supersampling at native resolution.
- Predictive MIP-level texture streaming. By inspecting internal attention maps, the network’s signal processor loads only the necessary low-resolution MIP levels into the L2 cache. This reduces video memory traffic, allowing the network to work directly with compressed texture tiles without unpacking them into a raw bitmap.
- Asynchronous WorkGraph execution pipeline. The upscaling and denoising passes are broken down into GPU task graph nodes, executed by the hardware scheduler. Idle SIMD waves between the main render and final composition are filled with FSR 4 operations without seizing compute units through forced barrier synchronization.
- Spatial adaptation to HDR stimuli. Tone mapping is integrated into the neural network’s latent space. The luminance map is normalized locally via a proposed Luminance-aware Activation module, which eliminates blocking artifacts at peak brightnesses exceeding 1000 nits, typical of SDR-trained models.
- Deterministic sampling noise. The network’s recurrent input is processed through a Blue Noise generator with a periodic mask based on a tile function. The biased high-frequency sequence eliminates flickering of thin parallel structures in motion, without requiring costly accumulation frame diversification.
- Low-level access via AMD FidelityFX API. The public SDK provides the FSR 4 Backend Interface extension. The developer manually substitutes depth, motion vector, and reactivity resources, disabling the driver’s internal heuristics for precise work with inverted Z-depth and custom transparency maps.
- Autonomous token skipping mechanism. The Token Skip sparse attention layer effectively discards computations for image fragments with zero variance. In flat shaded areas where the information gradient is minimal, the network traverses a shortened graph, saving up to 20% of stream processor resources.
- Final synthesis via HDR compositor. The output frame assembly is performed by a separate neural compositor that blends the upscaled image with transparent user interface elements. The compositor has a gamma curve independent from the game engine, preserving the sharpness of sub-pixel graphics over the processed 3D frame.
Comparisons
- FSR 4 vs DLSS 4 (CNN Model). FSR 4 is based on a fully hardware-accelerated ML model on the RDNA 4 architecture, unlike the software approach of FSR 3.1. Compared to the reference convolutional network DLSS 4 CNN, AMD’s solution demonstrates significant progress in geometry stability, eliminating pixel flickering but still lagging behind in complex scenes with fast-moving transparent textures.
- FSR 4 vs DLSS 4 (Transformer Model). AMD’s technology uses FP8 computations on specialized accelerators, increasing detail compared to CNN networks. However, Nvidia’s new transformer model shows superiority in ray reconstruction and preserving fine textures at ultra-high resolutions, while FSR 4 focuses on an effective balance between quality and rendering latency.
- FSR 4 vs Intel XeSS 2 (XMX). Both technologies utilize dedicated GPU matrix blocks for neural network inference aimed at upscaling. AMD’s implementation within RDNA 4 provides more aggressive anti-aliasing and lower overhead at low resolutions, while XeSS 2 on the Battlemage architecture benefits from low-latency frame generation and better noise suppression in deep shadows.
- FSR 4 vs PSSR (PlayStation Spectral Super Resolution). The specialized ML upscaler for PS5 Pro operates within a strict console power budget, optimizing for a single hardware configuration. The advantage of FSR 4 is open cross-platform compatibility with fine-tuning for the variable zoo of PC hardware, providing on RDNA 4 a higher frame rate headroom and clarity of distant objects than solutions based on RDNA 2.
- FSR 4 vs FSR 3.1 (Spatial Upscaling). The transition from a spatio-temporal algorithm to hardware-based machine intelligence completely changes the philosophy of pixel processing. FSR 4 gets rid of the artifacts characteristic of FSR 3.1, such as the disappearance of thin lines and depth of field instability, replacing heuristic filters with deep scene analysis and detail reconstruction comparable to native resolution.
OS and driver support
FSR 4 is implemented exclusively on the RDNA 4 hardware platform through the Adrenalin graphics driver software interface in the Windows environment, while the amd_fidelityfx_sdk library is integrated directly into the game’s executable file, and the activation of ML accelerators occurs via DirectX 12 Ultimate and Vulkan commands with driver digital signature verification at the graphics pipeline initialization stage.
Security
The FSR 4 machine learning model is loaded into a protected GPU memory region with hardware encryption; the integrity check of the neural network weights is performed via SHA-256 hash verification on the driver side before the start of inference; and the isolation of compute units prevents the game process from accessing the algorithm’s internal buffers through the RDNA 4 hardware scheduler.
Logging and diagnostics
The driver maintains structured logging of FSR 4 operation through Windows Event Tracing for Graphics channels, recording inference timestamps, ML accelerator occupancy, and the amount of allocated video memory in a ring diagnostic buffer, accessible to the developer via the GPU Performance API without impacting rendering performance.
Limitations
FSR 4 functions only on video chips with the RDNA 4 architecture, as it relies on specialized second-generation matrix accelerators with support for FP8 format and WMMA instructions, which are absent in previous generations, and the minimum local memory size for hosting the neural network context is 8 GB, which automatically cuts off lower-end adapter configurations.
Technology evolution
The development of FSR 4 began with an AMD research project to port the spatial-temporal scaling of FSR 3.1 to hardware-accelerated inference. Then, a dedicated ML computation block with direct access to the second-level cache was introduced in RDNA 4, which made it possible to replace manual anti-aliasing heuristics with neural network detail reconstruction trained on a high-resolution synthetic dataset.