What is WCB (Merging write operations in memory)

WCB (Write Combining Buffer) is a hardware buffer in the processor that accumulates multiple separate writes into a single linear group to send them as one burst transaction over the bus. This approach avoids the overhead of many small data transfers and significantly speeds up interaction with I/O devices.

Most often this mechanism is used when working with video memory of graphics cards (via memory regions with the Write-Combining type, marked by PAT or MTRR attributes) and when filling frame buffers. It is critically important for rendering functions, direct memory access of modern GPUs, and writing streaming data to network adapters, where the priority is throughput rather than strict ordering of individual writes.

The main challenge is related to the violation of strict instruction ordering: the buffer aggressively reorders and merges writes, so it is not suitable for devices with order-sensitive side effects (control registers). Incorrect usage can lead to situations where a final notification value reaches memory before the main data block write completes, and an attempt to read from a combined region causes a forced buffer flush and a sharp performance drop.

How WCB works

The principle of operation is based on intercepting store requests addressed to memory with the Write-Combining type. Instead of immediately seizing the bus and doing a write-through of each value, the processor checks whether the new address falls into the same 64-byte cache line as previous unsaved data inside the buffer. If there is a hit, the new data portion simply merges into the partially filled entry without waiting for a response from the device. On a miss, when a full line is completed, or when a barrier instruction (for example, SFENCE) is executed, the buffer is forcibly flushed as a single unordered burst transaction. Unlike ordinary combining in the cache (Store Buffer), which serves coherence and obeys strict ordering for cacheable memory, the Write Combining Buffer works specifically with uncacheable regions and deliberately sacrifices latency and ordering rules for maximum write throughput to relatively slow external interfaces.

WCB functionality

Purpose of the write combining buffer. Write Combining Buffer (WCB) is a hardware queue in the processor’s memory subsystem designed to aggregate partial non-coherent writes before sending them to main memory or I/O.
Uncacheable combinable memory. WCB is applied exclusively to memory regions marked as Write-Combining (WC) in page tables. Standard cacheable memory (WB) uses the write-back mechanism, while strictly uncacheable (UC) memory prohibits any combination.
Merging partial transactions. The main function of the buffer is to merge multiple unaligned or bus-width-incomplete writes into a single larger transaction, which minimizes bandwidth usage and the number of system bus busy cycles.
Temporary write delay. Data placed into the WCB does not leave the processor immediately. It is held in the accumulation buffer, waiting for subsequent writes to adjacent addresses, allowing the hardware to form a complete line for eviction to memory.
Buffer structure and capacity. Physically, the WCB consists of a small number of entries (often 4–8), each the size of one cache line (64 bytes). Each entry contains validity bits (byte mask) that define which data fragments are already filled.
Data eviction logic. Eviction of an entry from the WCB occurs upon a certain event: filling of the entire byte mask (completed line), address conflict, execution of a memory barrier (SFENCE/MFENCE), or when all available buffers are occupied by new streams.
Non-coherent nature of operations. Write combining buffers operate bypassing cache coherence protocols. The processor does not check for modified copies in the caches of other cores before eviction, which makes WC memory suitable only for one-way or synchronized communications.
Handling strict ordering. A write to strictly ordered memory (Strong Uncacheable) acts as a barrier: before executing such an instruction, all WCB buffers are forcibly drained, guaranteeing the observable order of operations in the x86 architecture.
x86 (Execution of instructions based on CISC architecture)
Semi-ordered propagation. Writes from the WCB can reach the system bus in an order different from the program order to achieve maximum throughput. This property requires developers to explicitly use barrier instructions to maintain ordering when interacting with devices.
Forced flush mechanisms. Besides the SFENCE and MFENCE instructions, WCB flushing can be triggered by uncacheable reads, bus lock operations (LOCK), execution of CPUID, and other events of context switch or deep sleep defined by the microarchitecture.
Byte masking and bus width. If a one-byte write arrives in the WCB, it does not generate an immediate transaction over an 8-bit bus, but sets the corresponding mask bit in the entry. Upon eviction, the entry will be sent as a whole burst transfer.
Protection against partial memory writes. The WCB guarantees that when an incomplete entry is evicted, the memory controller generates a correct byte mask signal. This prevents writing uninitialized (garbage) data to physical DRAM or MMIO device registers.
DRAM (Storage and Byte-addressing of Data)
Interaction with DMA devices. When filling a video card’s frame buffer via WCB, data can be held in the processor for a long time. For the direct memory access agent to see the actual data, the program must perform a buffer flush via a memory barrier.
Optimization for linear frame buffers. The most well-known application of WCB is writing textures to video memory. Writing pixels along the horizontal effectively merges into 64-byte lines, saturating the PCI Express bus and radically reducing delays compared to UC memory.
Mechanism of uncacheable speculative reads. Modern WCB implementations allow speculative prefetch from a WC region into special uncacheable read buffers, accelerating access to linear structures; however, the data is immediately invalidated after reading.
Internal replacement policy. On multiple misses to different physical addresses, pseudo-LRU or another heuristic is used. A WCB entry that is not fully combined but has not been updated for a long time will be evicted to free the buffer for a new address stream.
Locks and atomicity. Execution of atomic operations (LOCK prefix) on WC memory is architecturally prohibited and causes an exception (in memory operations). Barriers, not atomic modifications directly in I/O registers, are used for synchronization with devices.
Implementation on the ring bus. In processors with a ring interconnect bus, a flushed WCB forms a packet directed straight to the Home Agent of the memory controller, bypassing cache agent sections to ensure a transparent non-coherent write.
Filling on a write miss. Unlike the WB cache, when writing to a WC region the line is never read from memory for updating (Read-for-Ownership). The WCB simply accumulates new data, leaving non-overwritten bytes in their original state, intended for overwriting.
Invisibility to feedback. A standard uncacheable read from a WC region does not check the contents of incomplete WCBs. If a write was placed in the buffer but not flushed, an immediate subsequent read of that address will return old data from memory.
Software pitfalls. Using REP MOVS for copying to WC memory can lead to degradation, turning a burst write into a sequence of partial overlapping operations. Streaming store instructions (MOVNTI/MOVNTDQ) are optimal.

Comparisons

WCB vs Write-Through cache. WCB temporarily accumulates data for a burst write over a wide bus, whereas Write-Through immediately duplicates each transaction to main memory. The combining buffer minimizes the number of transactions and bus load, while write-through guarantees strict coherence at the cost of high delays and excessive bandwidth consumption on I/O operations.
WCB vs Write-Back cache. The combining buffer optimizes streaming writes to uncacheable memory (usually graphics) by aggregating individual byte instructions, whereas the Write-Back cache serves the processor by holding modified lines in cache lines. WCB reduces traffic during sequential non-maskable accesses to devices, while Write-Back reduces accesses to DRAM for reusable computational data through deferred line eviction.
WCB vs USWC range in MTRR. WCB is a hardware mechanism in the memory subsystem, while USWC is an attribute of a page or range in memory type range registers (MTRR/Pat) that prohibits speculative reads and allows combining. Designating a memory range as USWC enables the internal WCB logic for that address space, unlike a purely buffer approach where combining is implemented without explicit binding to uncacheable speculation at the page level.
WCB vs Store Buffer. The Store Buffer in the processor pipeline is responsible for speculative dependency removal during writes to cache memory with low latency, whereas the WCB acts as a capacious accumulator at the exit beyond the cache hierarchy. The store buffer operates on physical registers and addresses with short queues, while the combining buffer gathers many scattered partial writes into a single burst transaction for the peripheral bus.
WCB vs Non-Temporal Store. Non-temporal store instructions (MOVNTI) are aimed at bypassing the cache and often directly activate WCB filling, avoiding eviction of useful data. Here, WCB is the implementing aggregation mechanism, while Non-Temporal Store is a semantic instruction; together they form an end-to-end path for minimizing cache pollution, where the instruction initiates the stream and the buffer combines partial write masks into an efficient burst dump.

OS and driver support

The operating system manages memory caching policy through page table attributes (PAT) and memory type range registers (MTRR), setting the Write-Combining (WC) type for video memory or device buffers, and device drivers request WC regions through kernel APIs like MmAllocateContiguousMemorySpecifyCache for direct data placement, from where the hardware WCB gathers individual uncacheable writes into wide burst transactions over the PCI Express bus before flushing the buffer with commands like sfence.

Security

WCB does not participate in cache coherence, so speculative execution can read a partially formed line before its actual dispatch to the device, creating a window for leakage of confidential data from the temporary write buffer, which is partially mitigated by write barriers, strictly using MOVNT instructions for their intended purpose, and disabling combining for pages marked as encrypted in trusted execution environments.

Logging

The hardware nature of WCB leaves no traces in software logs, so debugging is implemented through hardware bus tracers, performance counters like wc_buffer_flushes in the processor’s PMU subsystem, and analysis of timing anomalies using logic analyzers on PCIe lines, comparing actual burst transfers with the expected combining pattern.

Limitations

A buffer of finite size (often one to two 64-byte lines) is forcibly flushed on a miss outside the combined range, which during interleaved writes to WC memory and ordinary memory degenerates into a sequence of single partial transactions with a flush delay after each instruction, completely negating the throughput gain.

Evolution

From the simplified unordered buffers of Pentium Pro, the architecture evolved to partially ordered pipelines with the ability of fused combining of non-coherent streams, and with the advent of UPI and CXL, the classic per-core buffer was replaced by distributed write agents that combine streams from multiple cores in a single routing node before dispatch to remote memory or an accelerator.