LFB (Cache Line Fill Buffer)

LFB (Line Fill Buffer) is a temporary storage in the processor where data from RAM arrives before loading into the cache. Until the line is fully filled, the processor waits but can read the needed byte early if it has already arrived, so as not to waste cycles on full waiting.

This mechanism is engaged on every miss past the L1 and L2 caches. It is critically important in high-load computing systems: database servers, physics simulation engines, and scientific calculations. It is actively used during sequential reading of large arrays, when the hardware prefetcher loads adjacent addresses, as well as during processing of streaming video and network traffic, where data arrives in irregular packets.

The main problem is latency due to unaligned memory access. If the requested byte physically arrives last in the packet, the processor stalls for tens of cycles. The situation is aggravated by contention: the number of buffers is limited (usually 10–12), and with parallel misses, a shortage occurs. Partial overwrites, when the core modifies only a piece of the line, create conflicts between reading and merging, which noticeably reduces memory subsystem throughput.

How LFB works

Upon receiving a request on a cache miss, the memory controller reserves a free buffer and sends the request onward. Memory returns data not instantly and not always sequentially: modern DRAM sends the so-called critical chunk first, then the remaining parts of the 64-byte line. The buffer, unlike the simple waiting registers of the Store Buffer, can track the arrival of individual segments and immediately pass the needed fragment to the execution unit without waiting for the entire line to fill. After complete assembly, the line is atomically moved to the L1 cache, and the buffer is freed.

If comparing LFB with Write Combining Buffer, the difference is fundamental: LFB is oriented towards reading and filling, allowing early pipeline wake-up, whereas Write Combining Buffer gathers scattered write operations into a single line for sending to memory without extra reads. Unlike Miss Status Holding Registers, which only store the state of the current miss, LFB physically accumulates bits. Compared to the streaming load mechanism in GPUs, where requests are masked through the warp scheduler, LFB works at the hardware level of the x86 core, providing a way to overlap memory latencies without thread context switching.

LFB functionality

1. Basic purpose of LFB. The Line Fill Buffer is a hardware queue in the processor core that accepts full 64-byte cache lines fetched from L2/L3 or memory. LFB serves as a link between the first-level cache subsystem and the rest of the hierarchy, temporarily storing data until it is committed to the L1D array.
2. Temporary storage for missed transactions. On an L1D read miss, an entry is created in the Fill Buffer, identified by a request identifier. This entry contains the physical address of the target line and a waiting state, reserving a slot until data is received from the cache fabric or memory controller, without blocking the pipeline.
3. Non-blocking execution of load instructions. The key function of LFB is the implementation of non-blocking first-level misses. While one load operation waits for a line fill, subsequent independent memory accesses that hit L1D successfully execute and retire results, masking the latency of the slow memory subsystem.
4. Connection with the memory ordering buffer. Data temporarily residing in LFB is logically considered part of L1D for the MOB mechanism. This allows speculative reads addressed to the awaited line to complete early via byte forwarding from the buffer without waiting for the physical write of the line into the cache data array.
5. Write merging mechanism. LFB performs hardware consolidation of multiple adjacent or overlapping write operations to the same cache line before its eviction. This technique, known as write combining, minimizes the number of transactions on the system bus and significantly increases throughput during streaming output.
6. Handling uncacheable memory types. When interacting with memory ranges marked as Uncacheable or Write-Combining, LFB serves as a partial buffering station. For the WC type, the buffer accumulates partial writes into one line for a subsequent burst flush, preventing an immediate costly single write to the bus for every byte.
7. Hardware prefetch into the buffer. Hardware code and data prefetchers, working at the junction of L2 and L1I/L1D, interact directly with LFB. The predicted line is loaded into a free buffer slot, not directly into L1. If the prediction turns out to be wrong, the filled slot is simply discarded without polluting the useful cache contents.
8. Coherency tracking and invalidation. LFB actively participates in coherency protocols. If an external agent or local core initiates a snoop request hitting the address of a line residing in the buffer, the coherency logic extracts or modifies the data directly in LFB, invalidating the slot before the physical insertion of the line into L1D.
9. Transformation of unaligned accesses. When a load instruction requests data crossing a 64-byte line boundary, two LFB slots are engaged. Both independent fill requests are tracked by the buffer until the missing fragments are assembled into a single result for transfer to the physical register file.
10. Properties on write-to-zero. Specialized instructions, like array initialization with zeros in REP STOSB, interact with LFB via a special protocol. Instead of reading the line before modification, a mechanism of writing an entire zero-value line directly from the buffer is used, implementing a read-for-ownership bypass at the architectural level.
11. Participation in speculative read operations. During a speculative load on an unresolved pointer address, an LFB slot is allocated, but the bus request may not be issued until resolution. If speculation turns out to be wrong during an order check, the slot is freed without initiating external traffic, isolating the memory subsystem from false triggers.
12. Interaction with store forwarding. Forwarding data from older store operations to younger loads has priority over LFB contents. If the load address matches an uncommitted store in the store buffer, the pipeline bypasses waiting for the main line and obtains the actual bytes directly from the Store Buffer, ignoring the stale state in LFB.
13. Power-dependent management and eviction. An LFB slot is not held indefinitely. Once the full line is received and the write bus to the L1D data array is free, the data is immediately committed. Under conditions of free slot shortage, backpressure is activated, halting the fetch of new instructions until the resource is freed.
14. Thread data stream partitioning. In architectures supporting simultaneous multithreading, LFB slots can be partitioned statically or dynamically between logical cores. This prevents a situation where one thread, generating frequent misses on page boundaries, occupies all buffer resources and starves the second thread.
15. Response to hardware virtualization. During nested page addressing, requiring double translation, LFB stores the line throughout the second-level table walk. In case of a guest abort of its deferred descent operation, the associated buffer state allows resuming the fill without rereading the upper-level entries.
16. Performance monitoring. The events resources fill and stall cycles due to buffer full directly indicate a deficiency in L1 throughput or the number of LFB slots. Analysis of these counters allows distinguishing DRAM latency from a microarchitectural bottleneck caused by the inability of the cache to accept incoming lines.
17. Emulation of uncacheable loads during copy. The technique of direct memory I/O temporarily places a line in LFB for direct register file servicing without polluting L1D. This emulates the behavior of an uncacheable load for large arrays, preserving temporal data in the cache during streaming copy.
18. Impact on memory barriers. A full memory barrier flushes the Store Buffer but does not invalidate active LFB slots. However, a serializing instruction guarantees that all preceding line fills are physically completed in L1D before the next read perceives the new architectural memory state.
19. Peculiarity of reading during unaligned atomic access. For atomic operations crossing a cache line boundary, the filling of two LFB slots occurs as an indivisible transaction in the memory subsystem. If slots cannot be allocated simultaneously, the pipeline stalls, preventing an observer from seeing a torn intermediate state.
20. Dependence on DCU fetch size. The line fill buffer is physically connected to the cache fabric, receiving lines in multiples of the Data Cache Unit fetch size. With adjacent line prefetch mode enabled, one slot can be associated with two neighboring requests, doubling the effective bandwidth during sequential access.
21. Flush on context change. Switching the address space via a write to CR3 does not cause a forced flush of LFB in modern implementations. However, the awakened process uses the LSb to tag the owner process to prevent data leakage through cross-snoop between different virtual environments relying on the same physical line.

Comparisons

• LFB vs L1 Data Cache. The line fill buffer interacts with the first-level data cache, not duplicates it. L1D stores data after full request completion, whereas LFB tracks uncompleted transactions on the bus, temporarily holding the just-received line until its write into the cache array, reducing latency for the load-waiting core.
• LFB vs Miss Status Holding Register (MSHR). MSHR logically manages the miss state and merges multiple requests to the same missing line, preventing repeated memory accesses. LFB functions as a physical receiving buffer accompanying each MSHR, directly storing the incoming parts of the line from the memory controller before atomic insertion into the cache.
• LFB vs Store Buffer (SB). The store buffer temporarily holds data and addresses of deferred write operations until their commitment in the memory hierarchy, providing write latency hiding and speculative execution. LFB, in contrast, works exclusively on reading during miss handling, buffering the incoming stream of lines fetched from RAM for load instructions.
• LFB vs Write Combining Buffer (WCB). Write combining buffers aggregate multiple uncacheable stores into one transaction to increase I/O throughput. Line fill buffers service cacheable read misses, and their main task is to minimize latency for dependent instructions by immediately forwarding data to the pipeline, bypassing the delay of a full cache tag write.
• LFB vs Fill Buffer in uncacheable memory. During a typical cacheable miss, LFB participates in allocating a new line. When working with uncacheable memory, specialized hardware structures are engaged, not standard LFBs. Here, the buffering of temporary data is often carried out in deeper ordering buffers, without subsequent filling of the cache array, preventing eviction of useful data and complying with memory side-effect semantics.

OS and driver support

The operating system manages LFB exclusively at the microarchitectural level through mechanisms of implicit data loading on L1 cache misses; no direct software interface exists for drivers, as the buffer is filled by the hardware prefetcher, and the kernel only sets policy via setting bits in MSRs (Model-Specific Registers) to disable filling when accessing memory ranges with uncacheable type (UC) or when working with MMIO regions, to prevent speculative reading on invalid physical addresses.

Security

The main vulnerability lies in the fact that LFB is a shared microarchitectural structure for all logical cores within a physical processor, which, during speculative execution, allows an attacker, through timing channel analysis (timing of accesses to cached and uncached data), to recover the buffer contents left after operations of another process or SGX enclave; hardware protection is implemented by clearing LFB on context switch or exit from speculative mode, as well as by partitioning the buffer into sections with security identifier tags.

Logging

Hardware logging of LFB events is performed through Performance Monitoring Counters, particularly events like L1D_PEND_MISS.FB_FULL, which record cycles during which the fill buffer was completely occupied and could not accept new requests from the core, as well as events counting the number of core stall cycles due to waiting for data fetch (resources_stall.sb), allowing profilers like perf and Intel VTune to detect bottlenecks in the memory subsystem.

Limitations

The key physical limitation of LFB consists of a fixed number of slots (usually 10 or 12 entries, each one cache line wide) in the cores of modern microarchitectures, which, under a large number of simultaneous misses, leads to filling all available lines and blocking further load operations until the current requests in the Super Queue complete, creating backpressure on the instruction pipeline and reducing the degree of Memory-Level Parallelism.

History and development

The development of LFB progressed from a simple write combining buffer (WCB) in the Intel P6 architecture, where it first appeared to smooth L2 cache latencies, to integration in modern cores with support for two-level prefetch logic based on linear filters and a stride detector, where the buffer now not only amortizes misses but also serves as a merge point for several speculatively initiated loads into one batched request to the memory controller for DRAM interface bandwidth utilization.