OISC is a processor that understands only one command instead of hundreds. Imagine that from an entire language only one word was left, which is sufficient for describing any actions. This single instruction, manipulating data in memory, is capable of reproducing the logic of the most complex programs through multiple repetition.
The concept is in demand in academic research and teaching computer architecture for demonstrating the principles of Turing completeness with a minimal set of means. In practice, OISC ideas are applied in the development of extremely simple control automata and cellular processors for tasks where minimal crystal area is important, not performance. Also, the architecture serves as a theoretical basis for some esoteric programming languages.
The main difficulty is catastrophically low performance due to the huge number of instructions for elementary actions and forced sequential data fetching. The load on the memory subsystem and bus bandwidth sharply increases. Programming becomes extremely non-intuitive, and the code size grows exponentially. The absence of hardware support for high-level constructs makes compilation incredibly complex, and debugging practically impossible without special tools.
How OISC works
Unlike traditional CISC or RISC architectures, where the control flow and arithmetic are divided among dozens of specialized commands, OISC reduces computations to one elementary operation, most often subtract and branch if less than or equal to zero (subleq). This instruction subtracts the content of one memory cell from another and, if the result turned out to be less than or equal to zero, transfers control to the third indicated address. Universality is achieved because by means of self-sufficient copying of values (emulation of addition through subtraction with a negative operand) and conditional jump, any constructs are modeled: loops, branches, and subroutine calls. Unlike multi-instruction machines, where addition is an atomic operation, here it is decomposed into a sequence of subtractions and transfers. Another common variant, move with branch if not zero (movfuscator), shifts the computational load exclusively onto the data transfer instruction, which at the same time checks the completion flag. Addressing in OISC is often flat, which turns the entire address space into a unified working field without division into registers and memory. Thus, the processor turns into a primitive but mathematically complete finite automaton, where the complexity of the algorithm is shifted from the hardware to the data structure and the sequence of addresses.
OISC functionality
- Format of the Subtract and Branch if Negative command. The instruction takes three operands: the address of the minuend A, the address of the subtrahend B, and the branch address C, forming an atomic cycle of reading, modifying, writing, and branching.
- Semantics of subtraction with conditional branch. The processor calculates the difference of values at addresses A and B, writes the result back into cell A, then analyzes the sign of the result to branch to instruction C upon a negative value.
- Encoding of unconditional branch. To realize a non-negative result that guarantees a branch, a cell with a deliberately zero value is used as the subtrahend B, which leaves the minuend A unchanged and always transfers control to C.
- Zeroing a register through self-destruction. The operation of writing zero into memory is achieved by subtracting a cell from itself: addresses A and B point to the same area, the difference zeroes the content, and a negative result is impossible.
- Emulation of the copy operation. Data movement is realized by zeroing the receiver through self-subtraction, then subtracting the negative value of the source from the cleared cell, inverting the sign through double application of SBN.
- Organization of addition arithmetic. Addition is modeled by inverting the sign of the subtrahend: first the cell is zeroed, then value B is subtracted from it, and the obtained negative result is subtracted from A, yielding the sum.
- Sign inversion through intermediate zero. Unary minus is created by subtracting the target variable from a cell previously zeroed by self-subtraction, which forms the twos complement of the number without a hardware negation block.
- Logical basis through arithmetic. Since any Boolean function is expressed through subtraction and sign check, the processor calculates conjunction and disjunction by manipulating the negative result flags without specialized logic gates.
- Implementation of indirect addressing. To access data by pointer, self-modifying code is used, where the address field of the SBN instruction is changed by subtracting an offset directly in the instruction stream stored in RAM.
- Mechanism of subroutine call. The return address is saved by subtracting a pre-prepared constant from the link cell, and the branch command modifies the instruction counter through an operation with a negative result.
- Hardware stack based on memory. The stack pointer is incremented and decremented by a sequence of subtractions of a unit constant, and push and pop operations are realized by copying data through a temporary storage cell.
- Working with jump tables. Multiple branching is built by calculating an offset through sequential subtractions and subsequent modification of the branch address in the executable instruction stored in the code line.
- Interpretation of the absence of a NOP operation. A no-operation instruction is synthesized by subtracting a zero operand from a cell with positive content, which guarantees no branch and data integrity, expending one cycle.
- Direct access to peripherals. Input-output devices are mapped onto the memory address space, so the SBN instruction reads the port at address A, modifies it, and sends it back, controlling external interfaces without separate IN and OUT commands.
- Paradigm of trigger architecture. An OISC analog using the single Move command with a pseudo-operation performs word transfer, and computations are entrusted to the ALU embedded in the data transfer path between memory and registers.
- ALU (Performs arithmetic and logical operations)
- Transport-triggered model of computation. The copy instruction moves operands into hidden registers of functional units, where addition or shift are triggered by the fact of writing, turning data transfer into the only type of operation.
- Subtractive MOVE model. Unlike SBN, computations are initiated by writing to special accumulator cells of the ALU, so the program consists of a sequence of transfers between memory and implicit operation registers.
- Synthesis of the comparison operation. The relation of two variables is determined by subtracting them from each other with sign preservation in an intermediate cell, then a series of conditional branches analyzes the negativity flag for equivalence and inequalities.
- Program counter as an operand. The control flow is changed by explicit subtraction of a constant from an accumulator cell associated with the address of the next instruction, which allows implementing a goto of arbitrary nesting without a hardware stack.
- Cyclic constructs and counters. Iteration is formed by an index cell, from which a unit is subtracted each pass; while the index is non-negative, the branch closes the loop body, and zeroing terminates the repetition.
- Turing completeness without microarchitectural excesses. The single SBN instruction proves computational universality through modeling a Minsky machine with two counters, where increment and decrement with zero check are expressed by a chain of subtractions.
- Modern interpretations of minimalism. The concept has evolved to SUBLEQ, where the branch is taken upon a zero or negative result, simplifying condition checking in loops and reducing the number of auxiliary instructions for logic inversion.
Comparisons
- MOVE vs OISC. In traditional architectures, the MOVE instruction copies data between registers or memory, requiring additional commands for arithmetic. In OISC, a single instruction, for example SUBLEQ, simultaneously performs subtraction, conditional branch, and data transfer, combining the functionality of MOVE with the control flow logic in one atomic operation.
- SUBLEQ vs OISC. SUBLEQ is the canonical implementation of OISC, where the instruction subtracts one value from another and performs a branch if the result is less than or equal to zero. Compared to other OISC approaches, SUBLEQ requires three addresses, which makes the code more compact, but increases decoding time and complicates pipelining implementation due to memory dependency.
- NAND vs OISC. An architecture based on the logical NAND operation is theoretically functionally complete, but requires explicit loading of operands and storing of the result. An OISC machine of the SUBLEQ type, on the contrary, integrates memory and control flow directly into the instruction semantics, which allows doing without a separate program counter, achieving Turing completeness in a more elegant, albeit slow, way.
- ZISC vs OISC. ZISC (Zero Instruction Set Computer) is based on a hardware neural network, where learning replaces programming, and pattern matching occurs without classical instructions. OISC preserves the von Neumann stored-program model, but reduces it to one primitive, which makes the system predictable and deterministic, unlike the probabilistic nature of ZISC.
- ZISC (Hardware nearest match search)
- SBN vs OISC. The SBN (Subtract and Branch if Negative) instruction is an alternative form of OISC, where the branch occurs upon a negative result. In comparison with SUBLEQ, a machine based on SBN requires a different compilation logic for arithmetic operations and loop organization, but retains the key advantage — the ability to implement an arbitrary algorithm through a single instruction type without loss of universality.
Execution of system calls
Interaction with the operating system is realized through a single subtract and branch instruction (SUBGE), where predefined memory areas are mapped to the kernel interface: writing the system call number and arguments into fixed cells with subsequent transfer of control triggers the handler, which reads the parameters, performs the operation, and places the return code in the accumulator register, while device drivers are controlled through the same memory model by mapping hardware registers onto the process address space with special access rights.
Isolation and access control
Security is based on combining a modified Harvard architecture and static code verification: memory is divided into non-overlapping code and data segments with hardware marking of pages as executable/non-executable, and each SUBGE instruction checks that the branch address belongs to an allowed range, while a privileged monitor analyzes the control flow graph before program launch, mathematically proving the absence of stack boundary overflows and the impossibility of code overwriting due to the absence of write instructions into the executable area.
Tracing and event audit
The logging subsystem uses a reserved range of physical addresses, writing to which is interpreted by the memory controller as a command to place a record into a cyclic hardware trace buffer: the program writes an event identifier and a timestamp through a standard subtraction operation into a mapped cell, and a separate coprocessor asynchronously reads this buffer, packs the data with the addition of a core identifier and a clock counter timestamp into non-volatile storage without stopping the main computational flow.
Limitations
The computational model imposes strict limitations on operation granularity: bit shifts and multiplication require the unrolling of program loops consisting of hundreds of SUBGE instructions with an exponential drop in performance, floating-point number processing is forcibly emulated through integer arithmetic in accordance with the IEEE 754 standard by manipulating the mantissa and exponent through tables of precomputed masks, and multitasking without a hardware scheduler is realized only by cooperative transfer of control through explicit saving of the task context into a dedicated memory region and an unconditional branch to the dispatcher with a catastrophic impact on response time.
Evolution
The history of development begins with the theoretical URISC model of Mavrodopoulos in 1988 and the practical implementation of SUBLEQ machines on FPGA matrices at the end of the nineties, then the vector shifted towards the area of ultra-minimalistic processors for embedded applications with provably safe execution time, and modern development is focused on creating multi-core OISC clusters with asynchronous message routing through the same subtraction instruction, where the address space of each core contains receive-transmit ports of neighboring network-on-chip nodes for massively parallel computations without increasing the complexity of the command decoder.